Pune o întrebare
  Tehnologie
andreipuiu
| andreipuiu a întrebat:

Codul in VHDL de mai jos imi numara din 1 in 1 si afiseaza pe un basys3 numarul. Stie cineva cum as putea sa il fac sa aiba ratia 3 in loc de 1? Am tot incercat sa modific, dar cand ajunge, de exemplu, la 9 imi numara inca 6 numere, pana la F.Ma poate ajuta cineva?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity seven_segment_display_VHDL is
Port ( clock_100Mhz : in STD_LOGIC;-- 100Mhz clock on Basys 3 FPGA board
reset : in STD_LOGIC; -- reset
Anode_Activate : out STD_LOGIC_VECTOR (3 downto 0);-- 4 Anode signals
LED_out : out STD_LOGIC_VECTOR (6 downto 0));-- Cathode patterns of 7-segment display
end seven_segment_display_VHDL;

architecture Behavioral of seven_segment_display_VHDL is
signal one_second_counter: STD_LOGIC_VECTOR (27 downto 0);
-- counter for generating 1-second clock enable
signal one_second_enable: std_logic;
-- one second enable for counting numbers
signal displayed_number: STD_LOGIC_VECTOR (15 downto 0):="0000000000000001";
-- counting decimal number to be displayed on 4-digit 7-segment display
signal LED_BCD: STD_LOGIC_VECTOR (3 downto 0);
signal refresh_counter: STD_LOGIC_VECTOR (19 downto 0);
-- creating 10.5ms refresh period
signal LED_activating_counter: std_logic_vector(1 downto 0);

signal first_digit: std_logic_vector(3 downto 0) := "0000";
--signal second_digit: std_logic_vector(3 downto 0):= "0000";
--signal third_digit: std_logic_vector(3 downto 0):= "0000";
--signal fourth_digit: std_logic_vector(3 downto 0):= "0000";

-- the other 2-bit for creating 4 LED-activating signals
-- count 0 >- 1 >- 2 >- 3
-- activates LED1 LED2 LED3 LED4
-- and repeat
begin
-- VHDL code for BCD to 7-segment decoder
-- Cathode patterns of the 7-segment LED display
process(LED_BCD)
begin
case LED_BCD is
when "0000" >= LED_out LED_out LED_out LED_out LED_out LED_out LED_out LED_out LED_out LED_out LED_out

0 Raportează Evaluează
Întrebări recente